Silicon Valley start-up Tilera has entered the heavy competition between AMD and Intel with an outstanding 64-core CPU with an embedded high-speed network that can pass up to 32 terabits of data a second between the various cores.
This is not a premiere, as Intel is already up in the front with an 80-core processor unveiled in February, whose overall size does not surpass that of a human nail and whose power consumption will be lower than most of today’s home appliances. Actually, even Tilera’s CEO Anant Agarwal admitted that “the Intel chip is conceptually similar to the Tile64” (the name of the new processor). However, while Intel envisions mass marketing of the 80-core marvel in about 5 years, samples of Tile64 are already in the hands of customers like 3Com or TopLayer, and Tilera is readying the first commercial chips for Q4 2007.
Tile64 is made up, as the name suggests, of tiles or identical processor cores interconnected with Tilera's iMesh on-chip network.
“Each tile is a complete full-featured processor, including integrated L1 & L2 cache and a non-blocking switch that connects the tile into the mesh. This means that each tile can independently run a full operating system, or multiple tiles taken together can run a multi-processing operating system like SMP Linux.
Tiles can be grouped into clusters to apply the appropriate amount of horsepower to each application. Since multiple operating system instances can be run on the Tile64 simultaneously, it can replace multiple CPU subsystems for both the data plane and control plane.”
The need for North Bridge or South Bridge for computer motherboards is eliminated (and the cost of implementing them too) through Tile64’s complete set of memory and Input/Output controllers, which also reduces the processing latency and the energy consumption.
Speaking of power efficiency, according to the technical specifications, idle tiles can be put into low-power sleep mode when unused, while the per-core consumption does not exceed 300mW (170-300mW). This makes the chip a leader in the performance-per-watt race.
Tilera’s engineers have successfully tackled one of the most difficult problems of CPU design: efficient communication between CPU cores. While speedier chips are always available through overclocking and while transistor counts have leapfrogged with the introduction of 65nm or even 45nm technology, buses and interconnects have evolved much slower, literally crippling the overall performance and forcing developers to “dumb down” their software applications.
"You lay out these cores much like you do tiles on a floor," said Anant Agarwal, Tilera founder and CEO, who is also an MIT professor. "By 2014, you will see a 1,000-core chip coming out."
According to the press release, The TILE64 family of processors has both the flexibility
and performance to support a wide range of computeintensive applications, including advanced networking, digital video, and telecom.
"This has some very clear kinds of applications for which it will be very well suited," said Nathan Brookwood, an analyst with Insight 64. "It stands a very good chance, especially in digital signal processing."
"The product they're talking about is not really targeted at general purpose computing," Brookwood said. "It would be great for cellphone tower base stations, much more than it's ever going to be a desktop processor or a server processor in a data center."
Tilera, which currently employs 64 people (coincidence maybe?...), has promised a cheaper 36-tile version of Tile64 for 2008, and a more powerful version, with 120 cores by 2009.
The Silicon Valley start-up, with $40 million in venture funding, said of its latest invention that it delivers 10 times the performance and 30 times the performance-per-watt of an Intel dual-core Xeon chip.
