AMD has a solid strategy for fighting Intel: strike when they least expect it! On August 15, one week ahead of this years’ Intel Developer Forum, AMD’s Senior Vice President Randy Allen presented plans for the shipping of its 45-nm chips by the fourth quarter of 2008.

On August 18, AMD offered very few details about its upcoming Shanghai processors, but they did say they should start shipping them in the second half of 2008. The processors will contain 6MB of Level 3 cache, compared with the 2MB of Level 3 cache of its quad-core Opteron processors.

The announcements came just as Intel prepares to bring the Nehalem processors to the market. The Nehalem processor family includes multiple processor cores and an integrated memory controller hub to improve performance. From AMD’s point of view however, Intel’s “innovations” are just mere imitations of AMD’s own innovations.

“They [Intel] won’t be factoring our 45-nanometer Shanghai product and be making shipments of that by the end of the year,” said Allen. “I think some of the questions that should be asked are, What is their [Intel’s] specific schedule for their two-socket offering around Nehalem and when is that going to make its way into the four-socket platforms?”

Nehalem will be equipped with 731 million transistors, up to 8 MB L3 cache, QuickPath Interconnect which will offer up to 25.6 GB per second and integrated memory controller. However, AMD said they have been using this features for the past five years. The Nehalem chips will be produced using Intel's 45-nanometer manufacturing process.

During the Intel ‘s Developer Forum, Intel is expected to announce details on the Nehalem architecture, known as Core i7. The company is also expected to ship 45-nm servers and high-end desktop chips based on Core i7 microarchitecture by the end of the year.